In general, as semiconductor devices become geometrically smaller, gate, source and drain regions are decreasing in size and the junction between the source region and the drain region needs to be shallower. However, for these reasons, undesirable high-resistance regions are generated.
Therefore, to reduce the resistance between the source and drain regions and a polycrystalline silicon region, a high melting point metal silicide is used on contacts between those regions.
Accordingly, whenever contacts between the source and drain regions and exposed silicon occur during processes, a thin film of high melting point metal is deposited and heated to form a silicide. In this process, various silicide compounds including platinum, manganese, cobalt, or titanium are used.
A method of fabricating a prior art semiconductor device will now be described referring to accompanying drawings.
FIGS. 1A to 1F are cross-sectional views illustrating a method of fabricating the prior art semiconductor device.
As shown in FIG. 1A, device isolation layers 22 are formed in the device isolation regions of a semiconductor substrate 21 having active regions and device isolation regions. The device isolation layers 22 are generally formed through a local oxidation of silicon (LOCOS) or shallow trench isolation (STI) process.
Then, the semiconductor substrate 21 is thermally oxidized at a high temperature to form a gate oxidation layer 23 on the semiconductor substrate 21.
A channel region of a transistor is formed by selectively implanting n-type or p-type impurity ions into the active region of the semiconductor substrate 21 to form an n-well or p-well (not shown). A thermal process is then performed thereon at a high temperature of about 1050˜1200° C.
Then, a polysilicon layer is deposited on the gate oxidation layer 23. The polysilicon layer and the gate oxidation layer 23 are selectively etched through a photolithography process to form a gate electrode 24.
As shown in FIG. 1B, n-type impurity ions or p-type impurity ions are implanted into the surface of the semiconductor substrate 21, using the gate electrode 24 as a mask, to form lightly doped drain (LDD) regions 25 at both sides of the gate electrode 24 in the surface of the semiconductor substrate 21.
As shown in FIG. 1C, an insulating layer is deposited on the surface of the semiconductor substrate 21 by a low pressure chemical vapor deposition (LPCVP) method; and an etch-back process is performed on the entire surface thereof to form insulating layer sidewalls 26 at both sides of the gate electrode 24.
Then, n-type or p-type impurity ions are implanted at high concentration into the surface of the semiconductor substrate 21, using the gate electrode 24 and the insulating layer sidewalls 26 as a mask, to form source-drain impurity regions 27 at both sides of the gate electrode 24 in the surface of the semiconductor substrate 21. A thermal process is then performed thereon at a temperature of about 1000˜1050° C.
Subsequently, a washing process is performed to remove from the semiconductor substrate 21 various target materials such as metal impurities, organic contaminants, and/or a natural oxidation layer.
Referring to FIG. 1D, the semiconductor substrate 21 having passed through the washing process is transferred to a sputter chamber (not shown) of sputtering equipment, and a metal layer 28 of, for example, cobalt, is sputtered and formed on the entire surface of the semiconductor substrate 21.
As shown in FIG. 1E, the semiconductor substrate 21 is then passed into rapid thermal process (RTP) equipment or an electric furnace, and is thermally processed at a temperature of 400˜600° C. to form a metal silicide layer 29 on the surface of the semiconductor substrate 21 including the gate electrode 24 and the source and drain impurity regions 27.
In particular, during the thermal process, silicon ions of the gate electrode 24 and the semiconductor substrate 21 react with metal ions of the metal layer 28, thereby forming the metal silicide layer 29. However, such a reaction does not occur in the insulating layer sidewalls 26 or the device isolation layers 22, and thus the metal layer 28 still remains thereon.
As shown in FIG. 1F, the remaining metal layer 28 on the insulating layer sidewalls 26 and the device isolation layers 22 is removed. Then the semiconductor substrate 21 is annealed at a predetermined temperature to stabilize a phase of the metal silicide layer 29, thereby completing a low-resistance metal silicide layer 29.
However, the related art method of fabricating a semiconductor device has the following problems.
That is, even though a polysilicon gate is advantageous for high-temperature processes, has excellent compatibility throughout the entire process, and shows excellent electrical properties after completion of device fabrication, high resistance occurs due to a super-high integration and a size decrease of the device. Moreover, the oxidation layer increases in thickness due to gate depletion, and the fluctuation of a threshold voltage occurs because of diffusion of dopants in the polysilicon gate.